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AND gate (CMOS: NAND + inverter)

Logic Gates from Components · free online experiment, runs in your browser with no install or sign-up.

Open this experiment in the circuit simulator

Objective

Build AND from a NAND followed by an inverter (six transistors).

Procedure

Use the Controls tab (or the batteries' Properties) to set each input to 0 V or 5 V and press Start Simulation; turn Live on and drag an input slider to watch the output.

Theory

AND = NOT(NAND): the extra inverter restores the polarity and also regenerates the logic levels.

Questions to answer

Why is a real AND gate slower than a NAND?

Components used

3 × 2N7000 N-MOSFET, 3 × BS250 P-MOSFET, 3 × Battery / DC source, LED 5mm Red, Panel voltmeter, Resistor 220 ohm 1/4W

About the model

Ideal wires; component models as listed in the catalogue (no parasitics, no temperature drift). Built without a breadboard so the schematic stays readable.