JK flip-flop (hold, set, reset, toggle)

Objective

Step a JK flip-flop through hold, set, reset and toggle on successive clock edges.

Procedure

1. Run and compare Q with the J and K patterns at each clock edge.

Theory

JK = 00 hold, 10 set, 01 reset, 11 toggle. Starting from Q = 0 the sequence 00, 10, 01, 11 gives Q = 0, 1, 0, 1; the next 00 holds Q = 1.

Questions to answer

1. What is the race-around condition?

Components used

Clock source, JK flip-flop, 3 × Logic probe / LED, 2 × Logic switch

About the model

Ideal wires; component models as listed in the catalogue (no parasitics, no temperature drift). Built without a breadboard so the schematic stays readable.

More Digital Systems Lab experiments

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