Mod-6 counter (asynchronous reset)

Objective

Make a counter that counts 0–5 by resetting a 4-bit counter as soon as it reaches 6.

Procedure

1. Run and read the count after each rising edge.
2. Use Q3·Q1 instead to build a mod-10 (decade) counter.

Theory

When the count becomes 6 (0110) the AND gate Q2·Q1 raises RESET and clears the counter immediately, so state 6 only exists as a very short glitch. The sequence is 0, 1, 2, 3, 4, 5, 0, …

Questions to answer

1. Why is the glitch on state 6 a drawback?

Components used

4-bit binary counter, AND, Clock source, 4 × Logic probe / LED

About the model

Ideal wires; component models as listed in the catalogue (no parasitics, no temperature drift). Built without a breadboard so the schematic stays readable.

More Digital Systems Lab experiments

• Serial-in parallel-out shift register
• Ring counter
• Johnson (twisted-ring) counter
• Serial sequence detector (1011)
• Truth tables of the basic gates