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Serial sequence detector (1011)
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Objective
Detect the pattern 1011 in a serial bit stream with a shift register and an AND gate.
Procedure
- Run: the stream 0 0 1 0 1 1 0 1 1 0 contains 1011 twice (overlapping).
Theory
The register holds the last four bits (Q3 = oldest). The output is 1 when Q3 Q2 Q1 Q0 = 1 0 1 1: AND(Q3, NOT Q2, Q1, Q0). Overlapping occurrences are detected too.
Questions to answer
- How would a Mealy FSM do the same with 3 states?
Components used
4-bit shift register, 3 × AND, Clock source, 2 × Logic probe / LED, Logic switch, NOT
About the model
Ideal wires; component models as listed in the catalogue (no parasitics, no temperature drift). Built without a breadboard so the schematic stays readable.
Open this experiment in the circuit simulator