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4-bit even-parity generator
Digital Systems Lab · free online experiment, runs in your browser with no install or sign-up.
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Objective
Generate an even-parity bit with an XOR tree: the parity output makes the total number of 1s even.
Procedure
- Run through all 16 data words and read P.
Theory
P = D3 ⊕ D2 ⊕ D1 ⊕ D0. The data plus parity always contain an even number of ones, so a single-bit error is detectable.
Questions to answer
- How does the receiver check parity?
Components used
Logic probe / LED, 4 × Logic switch, 3 × XOR
About the model
Ideal wires; component models as listed in the catalogue (no parasitics, no temperature drift). Built without a breadboard so the schematic stays readable.
Open this experiment in the circuit simulator