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Half adder (gates)

Digital Systems Lab · free online experiment, runs in your browser with no install or sign-up.

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Objective

Add two bits with an XOR gate (sum) and an AND gate (carry).

Procedure

  1. Run through the four input combinations and read SUM and CARRY.

Theory

SUM = A ⊕ B and CARRY = A · B. 1 + 1 = 10 in binary: sum 0, carry 1.

Questions to answer

  1. Why can a half adder not be chained?

Components used

AND, 2 × Logic probe / LED, 2 × Logic switch, XOR

About the model

Ideal wires; component models as listed in the catalogue (no parasitics, no temperature drift). Built without a breadboard so the schematic stays readable.

Open this experiment in the circuit simulator

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