D flip-flop

Objective

Show that a D flip-flop samples D on the rising clock edge and holds it in between.

Procedure

1. Run: D = 0 1 1 0 1 0 0 1; the clock rises at 0.5 s, 1.5 s, …
2. Compare Q with D just before each edge.

Theory

Q takes the value of D present at each rising edge and holds it until the next. Changes of D between edges have no effect.

Questions to answer

1. What is set-up time?

Components used

Clock source, D flip-flop, 3 × Logic probe / LED, Logic switch

About the model

Ideal wires; component models as listed in the catalogue (no parasitics, no temperature drift). Built without a breadboard so the schematic stays readable.

More Digital Systems Lab experiments

• JK flip-flop (hold, set, reset, toggle)
• 4-bit binary counter
• Mod-6 counter (asynchronous reset)
• Serial-in parallel-out shift register
• Ring counter