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4-bit ripple-carry adder
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Objective
Chain four full adders and add 7 + 5, 9 + 9, 15 + 1 and 6 + 3 (one per second).
Procedure
- Run and read S3…S0 and C4 for each of the four additions.
Theory
The carry ripples from bit 0 to bit 3: S = A + B (5 bits including the final carry C4). The delay grows with every stage.
Questions to answer
- What limits the speed of a ripple-carry adder?
Components used
4 × Full adder, 5 × Logic probe / LED, 9 × Logic switch
About the model
Ideal wires; component models as listed in the catalogue (no parasitics, no temperature drift). Built without a breadboard so the schematic stays readable.
Open this experiment in the circuit simulator