4:1 multiplexer from 2:1 multiplexers

Objective

Select one of four data inputs (1, 0, 1, 1) with a two-bit select code, using three 2:1 multiplexers.

Procedure

1. Run: the select lines count 00, 01, 10, 11 and the output follows D0 … D3.

Theory

Y = D[S1 S0]. The first rank of two multiplexers chooses between (D0, D1) and (D2, D3) with S0; the second rank chooses between the results with S1.

Questions to answer

1. How would you implement any 3-input function with an 8:1 mux?

Components used

3 × 2:1 multiplexer, Logic probe / LED, 6 × Logic switch

About the model

Ideal wires; component models as listed in the catalogue (no parasitics, no temperature drift). Built without a breadboard so the schematic stays readable.

More Digital Systems Lab experiments

• 2-to-4 line decoder
• D flip-flop
• JK flip-flop (hold, set, reset, toggle)
• 4-bit binary counter
• Mod-6 counter (asynchronous reset)