NOR gate (CMOS)

Objective

Build a CMOS NOR: two NMOS in parallel, two PMOS in series.

Procedure

1. Use the Controls tab (or the batteries' Properties) to set each input to 0 V or 5 V and press Start Simulation; turn Live on and drag an input slider to watch the output.

Theory

Either NMOS pulls the output low; only when both inputs are low are both series PMOS on and the output is high.

Questions to answer

1. Which network has the weaker drive: the series PMOS pair or the series NMOS pair?

Components used

2 × 2N7000 N-MOSFET, 2 × BS250 P-MOSFET, 3 × Battery / DC source, LED 5mm Red, Panel voltmeter, Resistor 220 ohm 1/4W

About the model

Ideal wires; component models as listed in the catalogue (no parasitics, no temperature drift). Built without a breadboard so the schematic stays readable.

More Logic Gates from Components experiments

• AND gate (CMOS: NAND + inverter)
• OR gate (CMOS: NOR + inverter)
• XOR gate (four CMOS NAND gates)
• Half adder from CMOS NAND gates
• Full adder from nine CMOS NAND gates