NAND gate (CMOS)

Objective

Build a CMOS NAND: two NMOS in series, two PMOS in parallel.

Procedure

1. Use the Controls tab (or the batteries' Properties) to set each input to 0 V or 5 V and press Start Simulation; turn Live on and drag an input slider to watch the output.

Theory

The series NMOS pair conducts only if both inputs are high (output low). If either input is low a PMOS connects the output to VDD. Pull-up and pull-down networks are duals.

Questions to answer

1. Why is NAND preferred over NOR in CMOS?

Components used

2 × 2N7000 N-MOSFET, 2 × BS250 P-MOSFET, 3 × Battery / DC source, LED 5mm Red, Panel voltmeter, Resistor 220 ohm 1/4W

About the model

Ideal wires; component models as listed in the catalogue (no parasitics, no temperature drift). Built without a breadboard so the schematic stays readable.

More Logic Gates from Components experiments

• NOR gate (CMOS)
• AND gate (CMOS: NAND + inverter)
• OR gate (CMOS: NOR + inverter)
• XOR gate (four CMOS NAND gates)
• Half adder from CMOS NAND gates