NOT gate (CMOS inverter)

Objective

Build a CMOS inverter from one N-MOSFET and one P-MOSFET.

Procedure

1. Use the Controls tab (or the batteries' Properties) to set each input to 0 V or 5 V and press Start Simulation; turn Live on and drag an input slider to watch the output.
2. Slide the input through 2–3 V and watch the output flip near 2.5 V.

Theory

Input high: the NMOS conducts and the PMOS is off, so the output is pulled to ground; input low: the PMOS conducts and the output is pulled to VDD. One transistor is always off, so no static current flows. The switching threshold is near VDD/2 = 2.5 V.

Questions to answer

1. Where does a CMOS gate dissipate power?

Components used

2N7000 N-MOSFET, BS250 P-MOSFET, 2 × Battery / DC source, LED 5mm Red, Panel voltmeter, Resistor 220 ohm 1/4W

About the model

Ideal wires; component models as listed in the catalogue (no parasitics, no temperature drift). Built without a breadboard so the schematic stays readable.

More Logic Gates from Components experiments

• NAND gate (CMOS)
• NOR gate (CMOS)
• AND gate (CMOS: NAND + inverter)
• OR gate (CMOS: NOR + inverter)
• XOR gate (four CMOS NAND gates)