NOT gate from an N-MOSFET with resistor load

Objective

Build an NMOS inverter: one MOSFET and a pull-up resistor.

Procedure

1. Use the Controls tab (or the batteries' Properties) to set each input to 0 V or 5 V and press Start Simulation; turn Live on and drag an input slider to watch the output.
2. Slide the input through 1.5–3 V: the output falls when it crosses the threshold.

Theory

Below the threshold (2.1 V) the transistor is off and the output is pulled to 5 V; at 5 V gate the MOSFET's on-resistance (~ 1.5 Ω) is far below the 10 kΩ load, so the output is ≈ 0 V. Power flows whenever the output is low.

Questions to answer

1. Why does CMOS use less power?

Components used

2N7000 N-MOSFET, 2 × Battery / DC source, Panel voltmeter, Resistor 220 ohm 1/4W

About the model

Ideal wires; component models as listed in the catalogue (no parasitics, no temperature drift). Built without a breadboard so the schematic stays readable.

More Logic Gates from Components experiments

• NOT gate (CMOS inverter)
• NAND gate (CMOS)
• NOR gate (CMOS)
• AND gate (CMOS: NAND + inverter)
• OR gate (CMOS: NOR + inverter)