NAND gate (DTL: diode-transistor logic)

Objective

Build a diode-transistor-logic NAND: a diode AND stage followed by a transistor inverter.

Procedure

1. Use the Controls tab (or the batteries' Properties) to set each input to 0 V or 5 V and press Start Simulation; turn Live on and drag an input slider to watch the output.

Theory

The input diodes form an AND at node X. A level-shifting diode plus Vbe needs X ≥ 1.4 V to turn the transistor on, so a low input (X ≈ 0.9 V) keeps it off with margin. Y = NOT(A·B).

Questions to answer

1. What is the noise margin of this gate?

Components used

3 × Battery / DC source, 3 × Diode 1N4007, Panel voltmeter, 3 × Resistor 220 ohm 1/4W, Transistor BC547 (NPN)

About the model

Ideal wires; component models as listed in the catalogue (no parasitics, no temperature drift). Built without a breadboard so the schematic stays readable.

More Logic Gates from Components experiments

• NAND gate (TTL with totem-pole output)
• NOT gate from an N-MOSFET with resistor load
• NOT gate (CMOS inverter)
• NAND gate (CMOS)
• NOR gate (CMOS)