NAND gate (TTL with totem-pole output)

Objective

Build a standard TTL NAND gate: multi-emitter input transistor, phase splitter and totem-pole output.

Procedure

1. Use the Controls tab (or the batteries' Properties) to set each input to 0 V or 5 V and press Start Simulation; turn Live on and drag an input slider to watch the output.

Theory

With any input low, the input transistor steals the base current of Q2, Q3 is off and Q4 pulls the output up (≈ 3.5 V). With all inputs high the current flows into Q2's base, Q3 saturates and the output is ≈ 0.2 V. The totem-pole gives low output impedance in both states. The multi-emitter transistor is two NPNs with common base and collector.

Questions to answer

1. Why is the TTL high level only about 3.4 V?

Components used

3 × Battery / DC source, Diode 1N4007, Panel voltmeter, 4 × Resistor 220 ohm 1/4W, 5 × Transistor BC547 (NPN)

About the model

Ideal wires; component models as listed in the catalogue (no parasitics, no temperature drift). Built without a breadboard so the schematic stays readable.

More Logic Gates from Components experiments

• NOT gate from an N-MOSFET with resistor load
• NOT gate (CMOS inverter)
• NAND gate (CMOS)
• NOR gate (CMOS)
• AND gate (CMOS: NAND + inverter)