NAND gate (transistors in series)

Objective

Build a 2-input NAND gate from two transistors in series.

Procedure

1. Use the Controls tab (or the batteries' Properties) to set each input to 0 V or 5 V and press Start Simulation; turn Live on and drag an input slider to watch the output.

Theory

The output is pulled low only if both transistors conduct (series path to ground): Y = NOT(A·B). The low level is the sum of the two saturation voltages (about 0.2–0.3 V).

Questions to answer

1. What happens to the low level with three transistors in series?

Components used

3 × Battery / DC source, Panel voltmeter, 3 × Resistor 220 ohm 1/4W, 2 × Transistor BC547 (NPN)

About the model

Ideal wires; component models as listed in the catalogue (no parasitics, no temperature drift). Built without a breadboard so the schematic stays readable.

More Logic Gates from Components experiments

• NAND gate (DTL: diode-transistor logic)
• NAND gate (TTL with totem-pole output)
• NOT gate from an N-MOSFET with resistor load
• NOT gate (CMOS inverter)
• NAND gate (CMOS)