NOR gate (RTL: resistor-transistor logic)

Objective

Build a 2-input NOR gate from two parallel transistors and a shared pull-up resistor.

Procedure

1. Use the Controls tab (or the batteries' Properties) to set each input to 0 V or 5 V and press Start Simulation; turn Live on and drag an input slider to watch the output.

Theory

Either transistor conducting pulls the shared collector node low: Y = NOT(A + B). Both low → both off → Y = 5 V.

Questions to answer

1. Why does the high level of RTL droop when several gates are connected to the output?

Components used

3 × Battery / DC source, Panel voltmeter, 3 × Resistor 220 ohm 1/4W, 2 × Transistor BC547 (NPN)

About the model

Ideal wires; component models as listed in the catalogue (no parasitics, no temperature drift). Built without a breadboard so the schematic stays readable.

More Logic Gates from Components experiments

• NAND gate (transistors in series)
• NAND gate (DTL: diode-transistor logic)
• NAND gate (TTL with totem-pole output)
• NOT gate from an N-MOSFET with resistor load
• NOT gate (CMOS inverter)